The synchronous
oscillator is an elegant but little known circuit which can be used to
advantage where a phase-locked loop (PLL) would normally be employed. The
SO is a free-running oscillator which oscillates at a frequency determined
by its LC tank with no signal applied to its input.
When a signal is applied within the SO's acquisition bandwidth the oscillator synchronises and tracks the input signal. The SO output amplitude is constant when locked to and tracking an input signal. A decrease in the input carrier-to-noise ratio reduces the SO's tracking bandwidth to maintain a constant signal-to-noise ratio at the SO's output. This characteristic allows a SO to acquire and track very noisy signals.
The SO can also act as a frequency multiplier or divider. In the direct sequence receiver, the SO locks to a noisy 12 MHz signal and provides a stable 6 MHz output. This function could be achieved using a PLL but the SO has many advantages5,6,7,8 and, as it is based on only two transistors, is much simpler to implement.
A simplistic explanation of the SO operation is that the upper transistor acts as a Class C oscillator. The upper transistor only conducts for a very brief period of time; when the upper transistor conducts, there is a voltage across the lower transistor biasing it allowing it to conduct. At this time the input signal can then be injected to synchronise the oscillator. During the rest of the oscillator cycle input noise is unable to enter the oscillator as the lower transistor is reverse biased. This arrangement produces coherent amplification which is why the SO can extract signals from very low signal-to-noise inputs.
Copyright James A. Vincent, 1993
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